Freescale dnes prezentoval nový mcu s jádrem Cortex M0+ (všimněte si prosím toho plus za M0!). Jádro M0+ je inovované jádro M0, změny jsou zaměřené na snížení dynamické spotřeby. Dle údajů od ARM je dynamická spotřeba jádra Cortex M0+ 11,2 uW/MHz v porovnání se spotřebou 16,36 uW/MHz dřívějšího jádra Cortex M0. Jádro Cortex M0+ se tedy stává velmi zajímavým kouskem v aplikacích se sníženou spotřebou. v další části tisková zpráva Freescale s podrobnostmi, video a něco podrobností o Cortex M0+.

Freescale Introduces Kinetis L Series, Industry’s First Microcontrollers Built on the ARM® Cortex-M0+ Processor

Alpha samples of entry-level Kinetis L series MCUs planned for Q2

AUSTIN, Texas,Mar. 13, 2012-- Highlighting its role as a leader in ARM®-based embedded processing, Freescale Semiconductor (NYSE: FSL) announced it will demonstrate its new Kinetis L series microcontrollers (MCUs) built on the ARM® Cortex™-M0+ processor at DESIGN West in San Jose, California. Alpha sampling of Kinetis L series devices will begin in the second quarter of 2012.

Freescale’s early demonstration of Kinetis L series devices is possible due to the close partnership between Freescale and ARM during the Cortex-M0+ core development process. Freescale was a lead partner, providing input that helped ARM define and develop the world’s most energy-efficient processor, designed to satisfy the rigorous energy-efficiency, cost-sensitivity and ease-of-use requirements of entry-level applications such as domestic appliances, portable medical systems, smart meters, lighting, power and motor control systems.

With more than 30 years of experience in MCU development, Freescale provided valuable insights during the definition and validation of the new processor, particularly in the areas of I/O handing and debug support. This close collaboration resulted in the L series – an entry-level MCU family that combines exceptional energy-efficiency and ease-of-use with the performance, peripheral sets, enablement and scalability of the Kinetis 32-bit MCU portfolio while leveraging the inherent low-power and high-performance features of the ARM Cortex architecture.

“Our close partnership with ARM throughout the design and development of their new core has positioned us as the first MCU supplier to produce and demonstrate an MCU based on the Cortex-M0+ and continues our strategy of driving to market new products based on the ARM architecture,” said Reza Kazerounian, senior vice president and general manager of Freescale’s Automotive, Industrial and Multi-Market Solutions Group. “Our new Kinetis L series MCUs will significantly expand the design options available for creating the next generation of smarter, smaller, more energy-efficient embedded applications.”

“Freescale was the first supplier to bring Cortex-M4 processor-based MCUs to the mass market, and they are again taking a lead role with an ARM processor – in this case the Cortex-M0+ processor,” said Mike Inglis, executive vice president and general manager of ARM’s Processor Division. “With the addition of the L series to their Kinetis line, Freescale is creating one of the industry’s broadest, most scalable ARM Cortex-M MCU portfolios, ranging from very low-cost, entry-level products based on the ARM Cortex-M0+ processor, up to 4 MB, 200 MHz devices based on the Cortex-M4 processor.”

Kinetis L series MCUs

Manufactured using Freescale’s low-leakage, 90 nm thin film storage (TFS) process technology, the Kinetis L series frees power-critical designs from 8- and 16-bit MCU limitations by combining excellent dynamic and stop currents with superior processing performance. A broad selection of on-chip flash memory densities and extensive analog, connectivity and HMI peripheral options enable increased intelligence for a range of applications.

The Kinetis L series also addresses the ease-of-use requirement critical for entry-level designs that is frequently a barrier to developers considering 32-bit solutions. Features within the MCU and in the accompanying enablement package will provide an easy look and feel, enabling quick access to new device capabilities. This will allow developers to leverage the full power of Kinetis L series MCUs, while maintaining the rapid development cycles common to entry-level designs.

Upward migration through the Kinetis portfolio is available via compatible Kinetis K series devices (built on the ARM Cortex-M4 processor) that provide access to DSP performance and advanced feature integration.

Full details of the Kinetis L series product families will be announced in June 2012 at the Freescale Technology Forum and accompanied by application-focused demos and in-depth customer training sessions. For more information, visit

ARM Cortex-M0+ processor

The ARM Cortex-M0+ processor evolves the previous-generation Cortex-M0 into a true 8-bit replacement, while maintaining compatibility with all other Cortex-M-class processors. This allows designers to reuse their existing compilers and debug tools. Enhancements to the new ARM Cortex-M0+ processor include:

A reduced two-stage pipeline, allowing faster branch instruction execution
Single-cycle access to I/O and critical peripherals
Optimized access to program memory
Linear 4 GB address space that removes the need for paging, reducing software complexity and ensuring a more 8-bit-like user experience
Micro trace buffer, providing a low-cost trace solution that allows faster bug identification and correction without the need for additional I/O resources.

Comprehensive enablement

As entry-level applications migrate from 8- and 16-bit to Kinetis 32-bit MCU solutions, the need for tightly integrated enablement resources is essential to fully leverage the new system resources. The Kinetis L series will benefit from a comprehensive enablement package standard for Kinetis devices, consisting of the Freescale CodeWarrior IDE, MQX RTOS and associated middleware, as well as support from the extensive ARM ecosystem.

Demonstration at DESIGN West

Freescale will demonstrate the ARM Cortex-M0+ core at its exhibition booth #1604 at DESIGN West, March 26-29 at the San Jose McEnery Convention Center.


O nové řadě Kinetis L hovoří Geoff Lees od Freescale.

Parametry Cortex M0+ jádra

ARM Cortex-M0+ Features

ISA SupportThumb® / Thumb-2 subset
Pipeline2 stage
Performance Efficiency1.77 CoreMark/MHz - 0.93 DMIPS/MHz (RVCT 5.0.90 compiler)
Memory ProtectionOptional 8 region MPU with sub regions and background region
InterruptsNon-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Sleep ModesIntegrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with ARM Power Management Kit
Bit ManipulationBit banding region can be implemented with Cortex-M System Design Kit
Enhanced InstructionsHardware single-cycle (32x32) multiply option
DebugOptional JTAG & Serial-Wire Debug Ports. Up to 4 Breakpoints and 2 Watchpoints
TraceOptional Micro Trace Buffer


Na webu ARM naleznete informace o Cortex M0+ zde.
Cortex M0+ Intro (pdf) zde.